1. Field of the Invention
The present invention relates to semiconductor devices and a method of manufacturing the same, and more particularly, to a semiconductor device having an MOS (Metal Oxide Semiconductor) transistor using an SOI (Silicon on Insulator) structure (hereinafter referred to as an "SOI-MOSFET") and a method of manufacturing the same.
2. Description of the Background Art
With remarkable spread of information apparatuses such as computers in recent years, demand for semiconductor devices has been rapidly increased. In a functional aspect, a semiconductor device of a large storage capacity which can operate at a high speed has been required. Accordingly, a technical development relating to integration, a high response rate, or high reliability of a semiconductor device has been advanced.
A DRAM (Dynamic Random Access Memory) is generally known as a semiconductor device, which can carry out random input/output of storage information. The DRAM includes a memory cell array serving as a storage region storing a plurality of pieces of storage information, and peripheral circuits required for carrying out input/output to and from the outside.
A configuration of the DRAM will be described hereinafter.
FIG. 30 is a block diagram showing a configuration of a general DRAM.
Referring to FIG. 30, a DRAM 650 includes a memory cell array 651, a row and column address buffer 652, a row decoder 653, a column decoder 654, a sense refresh amplifier 655, a data in buffer 656, a data out buffer 657, and a clock generator
Memory cell array 651 serves to store a data signal of storage information. Row and column address buffer 652 serves to receive an address buffer signal externally for selecting a memory cell configuring a unit storage circuit. Row decoder 653 and column decoder 654 serve to designate a memory cell by decoding the address buffer signal. Sense refresh amplifier 655 serves to amplify and read out a signal stored in the designated memory cell. Data in buffer 656 and data out buffer 657 serve to input or output data. Clock generator 658 serves to generate a clock signal.
Memory cell array 651 occupies a large area on a semiconductor chip of the DRAM configured as described above. Memory cell array 651 includes a plurality of memory cells for storing unit storage information arranged in a matrix manner.
FIG. 31 is an equivalent circuit diagram for four bits for explaining a configuration of the memory cell array. Referring to FIG. 31, a memory cell generally includes one MOS transistor 610 and one capacitor 630 connected thereto. The memory cell is widely known as a one-transistor/one-capacitor type memory cell. A memory cell having such a configuration is widely used in a DRAM of a large capacity, since it is easy to improve integration of a memory cell array because of its simple structure.
FIG. 32 is a cross section showing schematically a conventional semiconductor device using an SOI-MOSFET as one-transistor/one-capacitor type memory cell. FIG. 33 is a schematic cross section taken along the line H--H of FIG. 32. Referring to FIGS. 32 and 33, an insulating layer 613 is formed on the entire surface of a silicon substrate 611. Silicon layers 601 are formed as islands on the surface of insulating layer 613 MOS transistor 610 is formed using silicon layers 601 on insulating layer 613 (i.e., using an SOI structure).
MOS transistor 610 includes a gate electrode 603, a gate insulating layer 605, and a pair of source/drain regions 607. The pair of source/drain regions 607 are formed on silicon layer 601 with a predetermined space. Source/drain region 607 has an LDD (Lightly Doped Drain) structure. More specifically, source/drain region 607 is in a two-layered structure of an impurity region 607a of a relatively low concentration and an impurity region 607b of a relatively high concentration. Gate electrode 603 is formed on a region sandwiched by the pair of source/drain regions 607 with gate insulating layer 605 interposed therebetween. An insulating layer 617 is formed on silicon layer 601 so as to cover the surface of gate electrode 603.
A first interlayer insulating layer 619 is formed on the entire surface of insulating layer 613 so as to cover MOS transistor 610. A contact hole 619a reaching one of the pair of source/drain regions 607 is formed in first interlayer insulating layer 619. A capacitor 630 is formed so as to be electrically connected to source/drain region 607 through contact hole 619a.
Capacitor 630 includes a lower electrode layer 621, a capacitor insulating layer 623, and an upper electrode layer 625. Lower electrode layer (storage node) 621 is formed on first interlayer insulating layer 619 in contact with source/drain region 607 through contact hole 619a. Capacitor insulating layer 623 is formed so as to cover the surface of lower electrode layer 621. Upper electrode layer (cell plate) 625 is formed so as to cover lower electrode layer 621 with capacitor insulating layer 623 interposed therebetween.
A second interlayer insulating layer 631 is formed on the entire surface of first interlayer insulating layer 619 so as to cover capacitor 630. The first and the second interlayer insulating layers have a contact hole 631a provided reaching the other of the pair of source/drain regions 607 therethrough. A bit line 641 is formed on second interlayer insulating layer 631 in contact with source/drain region 607 through contact hole 631a.
A third interlayer insulating layer 645 is formed on the entire surface of second interlayer insulating layer 631 so as to cover the surface of bit line 641. A plurality of aluminum interconnection layers 637 patterned into a desired shape are formed on the surface of third interlayer insulating layer 645.
In such an SOI-MOSFET as described above, the space between interconnection of capacitor 630, bit line 641 or the like and silicon substrate 611 is increased by the thickness of insulating layer 613. Therefore, a capacity between interconnection and substrate, that is, a so-called interconnection capacity is reduced, and an operating speed of the circuit is increased. When such an SOI-MOSFET is applied to a CMOS, a latch-up phenomenon can also be prevented. Such an SOI-MOSFET applied to a CMOS has various advantages such as reduction of a short channel effect, improvement of a current driving ability, improvement of a subthreshold characteristic.
Therefore, when such an SOI-MOSFET is applied to a memory cell of a DRAM, a device of high reliability can be obtained in which software and latch-up are restrained, and in which a refresh characteristic is improved.
In the configuration of the conventional semiconductor device, however, MOS transistor 610, capacitor 630, and bit line 641 are formed on different layers, which causes the following problems.
Referring to FIG. 33, islands of silicon layer 601 are formed on insulating layer 613. A surface stepped portion is formed at the boundary of silicon layer 601 and insulating layer 613. Therefore, a surface stepped portion affected by the underlying stepped portion appears in first interlayer insulating layer 619 covering the stepped portion.
Lower electrode layer 621 patterned into a desired shape is formed on the surface of first interlayer insulating layer 619 having the surface stepped portion. A stepped portion is also formed at the boundary of lower electrode layer 621 and first interlayer insulating layer 619. More specifically, a stepped portion is further formed on the surface stepped portion of interlayer insulating layer 619. Second interlayer insulating layer 631 covering the stepped portion has a surface stepped portion larger than that of first interlayer insulating layer 619. As described above,i when conductive layers of devices, interconnections or the like are multi-layered, the surface stepped portion becomes more significant at the upper interlayer insulating layer out of interlayer insulating layers insulating these conductive layers.
In the conventional memory cell structure, as described above, MOS transistor 610, capacitor 630, and bit line 641 are formed on different layers. These conductive layers are in a three-layered structure. Therefore, the surface stepped portion of top interlayer insulating layer 645 becomes large. When interconnection layer 637 is patterned on interlayer insulating layer 645 having such a large surface stepped portion, it is quite difficult to pattern the interconnection layer into a desired shape. Interconnection layer 637 might be deteriorated in shape or disconnected.
FIG. 34 is a schematic plan view for explaining disconnection or deterioration in shape of the interconnection layer when the underlaying surface stepped portion is large. FIG. 35 is a schematic cross section taken along the line J--J of FIG. 34.
Referring to FIGS. 34 and 35, when the interconnection layer is formed by patterning, conductive layer 637 serving as the interconnection layer is formed on the entire surface of third interlayer insulating layer 645. Photoresist 647 is applied onto conductive layer 637. Only a desired portion 647b of photoresist 647 is exposed, whereby a resist pattern 647b of a desired shape is formed.
If there is a surface stepped portion on the underlying layer of a region 647b to be exposed, however, a region 647a not to be exposed is also exposed at the time of exposure of photoresist 647, causing deterioration in shape of the resist pattern.
In particular, in a recessed portion 645a surrounded by a projection as shown in FIG. 34, exposure light is reflected at a sidewall portion at the boundary of the projection and recessed portion 645a. As a result, exposure light is converged on the center portion of recessed portion 645a, causing a so-called convex mirror phenomenon. When the convex mirror phenomenon occurs, portion 647a serving as a resist pattern of photoresist 647 is substantially exposed. A large defect or the like of the pattern appears on resist pattern 647a, causing deterioration in shape of resist pattern 647a.
When conductive layer 637 is etched away with resist pattern 647a deteriorated in shape used as a mask, interconnection layer 637 deteriorated in shape, for example, partially reduced in width, is formed as shown in a plan view of FIG. 36. In the worst case, interconnection layer 637 may be disconnected. When interconnection layer 637 is thus deteriorated in shape, the interconnection resistance of interconnection layer 637 increases. When interconnection layer 637 is disconnected, interconnection layer 637 no longer serves as interconnection.